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- Ekachai Lelarasmee, Albert E. Ruehli, Alberto L. Sangiovanni-Vincentelli
- IEEE Transactions on Computer-Aided Design of…
- 1982

The Waveform Relaxation (WR) method is an iterative method for analyzing nonlinear dynamical systems in the time domain. The method, at each iteration, decomposes the system into several dynamical subsystems each of which is analyzed for the entire given time interval. Sufficient conditions for convergence of the WR method are proposed and examples in MOS… (More)

- Narasimha R. Adiga, George Almási, +111 authors K. Yates
- SC
- 2002

This paper gives an overview of the BlueGene/L Supercomputer. This is a jointly funded research partnership between IBM and the Lawrence Livermore National Laboratory as part of the United States Department of Energy ASCI Advanced Architecture Research Program. Application performance and scaling studies have recently been initiated with partners at a… (More)

Inductance effects in on-chip interconnects have become significant for specific cases such as clock distributions and other highly optimized networks [1,2]. Designers and CAD tool developers are searching for ways to deal with these effects. Unfortunately, accurate on-chip inductance extraction and simulation in the general case are much more difficult… (More)

- Phillip Restle, Albert E. Ruehli, Steven G. Walker, George Papadopoulos
- IEEE Trans. on CAD of Integrated Circuits and…
- 2001

- Mohammad Al-Khaleel, Albert E. Ruehli, Martin J. Gander
- IEEE Trans. on Circuits and Systems
- 2009

—Waveform relaxation (WR) is a technique which can be used to solve large systems of ordinary differential equations (ODEs). It is especially suitable for the parallel solution of ODEs with multiple time scales, and has been successfully used for solution of electronic circuits and for solving partial differential equations (PDEs). The main issue limiting… (More)

- Eli Chiprout, Hansruedi Heeb, Michel S. Nakhla, Albert E. Ruehli
- ICCAD
- 1993

With ever increasing clock frequencies, accurate 3-D interconnect analysis in chips and packages is becoming a necessity. The retarded partial element equivalent circuit (rPEEC) method has been successfully applied to 3-D analysis but for large problems at becomes expensive in CPU and memory usage, and in time domain it sometimes has numerical problems.… (More)

—The increase of operating frequencies requires 3-D electromagnetic (EM) methods, such as the partial element equivalent circuit (PEEC) method, for the analysis and design of high-speed circuits. Very large systems of equations are often produced by 3-D EM methods and model order reduction (MOR) techniques are used to reduce such a high complexity. When… (More)

Waveform relaxation techniques are an important tool for the simulation of very large scale circuits. They are based on a partition of the circuit into sub-circuits, and then use an iteration between sub-circuits to converge to the solution of the entire circuit. Their importance has increased with the wide availability of parallel computers with a large… (More)

—Electromagnetic solvers based on the partial element equivalent circuit (PEEC) approach have proven to be well suited for the solution of combined circuit and EM problems. The inclusion of all types of Spice circuit elements is possible. Due to this, the approach has been used in many different tools. Most of these solvers have been based on a rectangular… (More)

A method for logic gate delay assignment is described which achieves power minimization of digital logic while satisfying system timing. The logic gates are described by a single design parameter macromodel. A Newton optimization scheme is employed using exact sparse updating. Systems consisting of up to 1200 digital logic gates have been optimized. A… (More)