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Recently, structured methods for solving factored Markov decisions processes (MDPs) with large state spaces have been proposed recently to allow dynamic programming to be applied without the need for complete state enumeration. We propose and examine a new value iteration algorithm for MDPs that uses algebraic decision diagrams (ADDs) to represent value(More)
The role of automatic formal protocol veriica-tion in hardware design is considered. Principles are identiied that maximize the beneets of protocol veriication while minimizing the labor and computation required. A new protocol description language and veriier (both called Mur') are described , along with experiences in applying them to two industrial(More)
Improvements in semiconductor technology now enable chip multiprocessors (CMPs). As many future computer systems will use one or more CMPs and support shared memory, such systems will have caches that must be kept coherent. Coherence is a particular challenge for multiple-CMP (M-CMP) systems. One approach is to use a hierarchical protocol that explicitly(More)
BDDs (binary decision diagrams) are ubiquitous in formal verification<lb>tools, and the time and memory used by the BDD package is frequently the con-<lb>straint that prevents application of formal verification. Accordingly, several re-<lb>searchers have investigated using parallel processing for BDDs. In this paper, we<lb>present a parallel BDD package(More)
It is well known that it is insecure to use the access(2) system call in a setuid program to test for the ability of the program’s executor to access a file before opening said file. Although the access(2) call appears to have been designed exactly for this use, such use is vulnerable to a race condition. This race condition is a classic example of a(More)
In previous work, Hu and Dill identified a common cause of BDD-size blowup in high-level design verification and proposed the method of implicitly conjoined invariants to address the problem. That work, however, had some limitations: the user had to supply the property being verified as an implicit conjunction of BDDs, the heuristic used to decide which(More)
Parameterized heuristics abound in computer aided design and verification, and manual tuning of the respective parameters is difficult and time-consuming. Very recent results from the artificial intelligence (AI) community suggest that this tuning process can be automated, and that doing so can lead to significant performance improvements; furthermore,(More)
Many researchers have reported that the use of Boolean decision diagrams (BDDs) greatly increases the size of hardware designs that can be formally verified automatically. Our own experience with automatic verification of high-level aspects of hardware design, such as protocols for cache coherence and communications, contradicts previous results; in fact,(More)