Akira Kanuma

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This paper presents a new non-robust delay fault test generation method for the purpose of screening delay defects of microprocessors with fewer test vectors. It is important to reduce the number of test vectors in order to reduce test time, memory usage in the tester, and the overall testing cost. By paying attention to the constraints of off-path inputs(More)
This paper presents a design methodology that was applied to the design of a 2.4GHz dual-core SPARC64 TM microprocessor with 90nm CMOS technology. It focuses on the newly adopted techniques, such as efficient data management in dual-core design, fast delay calculation of the noise-immune clock distribution circuit, enhanced signal integrity analysis of a(More)
This paper presents a case-study of delay defect screening applied to Fujitsu 2.16GHz SPARC64 microprocessor. A non-robust delay test is used while each test vector is compacted to detect multiple transition faults in a standard scan-based design targeting a stuck-at fault test. Our test technique applied to a microprocessor designed with 6M gate logic, 4MB(More)
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