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We present a gate delay model of CMOS logic gates driving a CRC load for deep sub-micron technology. Our approach is to replace series-parallel connected MOSFETs to an equivalent MOSFET and calculate the output waveform by an analytically derived formula. We present a MOSFET drain current model improved from the n-th power law MOSFET model to represent the… (More)

- Akio Hirata, Hidetoshi Onodera, Keikichi Tamaru
- 1998

We present a gate delay model of CMOS logic gates driving a CRC load for deep sub-micron technology. Our approach is to replace series-parallel connected MOSFETs to an equivalent MOSFET and calculate the output waveform by an analytically derived formula. We present a MOSFET drain current model improved from the-th power law MOSFET model to represent the… (More)

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