Akinori Kanasugi

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In recent years, demand for field-programmable gate arrays (FPGAs) has increased significantly. Designed similarly to software, FPGAs opened the door to the field of hardware for many people. However, developing a circuit using conventional methods is time consuming. In this paper, we propose a processor generator that can shorten development time and(More)
This paper proposes hardware implementation of evolutionary algorithms using dynamic reconfiguration technology. In this paper two types of dynamic reconfiguration for evolutionary algorithm are introduced. The processor was designed by using VHDL and the circuit was simulated. The effectiveness of the proposal processor was confirmed.
In this paper, we propose a position detection method for a microwell with manageable volume (MMV) chip on the stage of the inverted microscope. When the manipulation robot arm puts an MMV chip on the microscope stage, there is alignment error up to 500 μm. This error affects measurement accuracy of fluorescence from solution filled in a tiny hall of the(More)
The aim of our study is implementation of genetic algorithm (GA) in FPGA hardware. We use GA for obtaining floating-point solutions accurately. For this purpose, we propose applying a gray-coded floating-point format to GA to improve accuracy of the solutions. In this paper, we show the result of simulations using a gray-coded floating-point format. We(More)
Multiply-accumulate operation is the most fundamental operation in digital signal processing for image processing, robotics and automatic control. In this paper, a novel architecture of dynamically reconfigurable fused multiply-adder (FMA) is proposed. Dynamic reconfiguration is a method that can change the circuit configuration without stop of operation.(More)