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—A new 400-Gb/s (100-Gb/s×4) physical-layer architecture for the next-generation Ethernet—using 100-Gb/s serial (optical single wavelength) transmission—is proposed. For the next-generation 400-Gb/s Ethernet, there are additional requirements from the market, such as power reduction and further compactization in addition to attaining even higher(More)
The world's first CMOS "gearbox LSI" based on 65-nm CMOS technology-namely, a 2-W 100-gigabit-Ethernet gearbox LSI combining a 10:4 multiplexer and a 4:10 demultiplexer-was developed. Its power consumption is 75% lower than that of a conventional SiGe-based gearbox LSI. The power consumption of its 12.5-Gb/s interface is 0.98 mW/(Gb/s), while that of its(More)
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