Ajoy K. Bose

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<bold>This paper describes a multiple delay simulator for MOS LSI circuits. The basic primitives for this simulator are MOS transistor structures where the transistors are evaluated logically. Integer rise and fall delays are associated with each transition and these delays are computed automatically based on device characteristics and circuit capacitances.(More)
Bridge is a behavioral synthesis system being developed at AT&amp;T Bell Laboratories. Two slicing techniques are implemented in this system to drive structural allocation; one is local slicing and the other is global slicing. Global slicing supports the synthesis of concurrent processes with a centralized control. A variable in a behavioral description can(More)
In this paper, we will present algorithms developed for an advanced fault simulation system in the MOTIS simulation environment. In particular, the algorithm to perform fault modeling and collapsing is first reviewed. Efficient algorithms to perform fault simulation are discussed in terms of fault list manipulation and primitive evaluation. The simulator(More)
<bold>This paper describes a fault simulator for MOS LSI circuits. The basic primitives for this simulator are MOS transistor structures where the transistors are evaluated logically. The simulator provides the capability of modeling and simulating both the classical input/output stuck-at faults and the non-classical transistor stuck-on and stuck-open(More)
<bold>To provide flexibility and efficiency in logic and timing verification of MOS VLSI circuits, it is desirable that various portions of a circuit can be described and simulated at appropriate levels of detail. Such a capability is provided by the Mixed-Mode Simulator described here. This simulator allows different elements of a circuit to be modeled and(More)
<bold>This paper describes a data structure to represent the driver-load configurations in MOS circuits, which is used universally in the MOTIS simulation environment. In particular, the data structure is used in mixed-mode evaluation including timing, and multiple/unit delay. Other applications include automatic delay calculation, transistor fault(More)
<bold>This paper describes a system of design aids which are used in the modeling and simulation of bipolar gate arrays for applications where the delays cannot be neglected. Prewired function blocks composed of circuit elements such as transistors, resistors, diodes, etc. are automatically converted to logic gate descriptions. The transistor level model of(More)
Some aspects of the application of functional simulation to fault diagnosis are discussed. A technique for functional simulation that preserves a high level of accuracy is described. Applicability of this method to fault simulation and diagnosis is shown by presenting an approach to diagnostic testing and giving an algorithm for test point placement. The(More)