Ajith Amerasekera

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A DSP-based low-power 12.5Gb/s SerDes using a baud-rate ADC and a digital data-path is developed for backplane data communication. A digital 2-tap FFE and a 5-tap DFE in the RX provide channel compensation. A BER of &lt;10<sup>-15</sup> is measured over legacy backplanes with 24dB loss at Nyquist. The power consumption and die area are 330mW and(More)
In order to realize a digital system with no distinction between &#x201C;on&#x201D; and &#x201C;off,&#x201D; the computational state must be stored in nonvolatile memory elements. If the energy cost and time cost of managing the computational state in nonvolatile memory can be lowered to the microsecond and picojoule-per-bit level, such a system could(More)
The high current and ESD effects on VLSI interconnect metallization have been characterized and a model for heating under ESD conditions is presented. I t is shown that thermal breakdown occurs when the resistances increase by a factor of >3.6 due to melting of metal lines. After the metal is molten, the thermal stress is required to exceed the fracture(More)
This work presents a detailed microanalysis of interconnect failure mechanisms under short-pulse stress conditions arising during peak current and electrostatic discharge (ESD) events. TEM and SEM analysis have been used to show that passivated AlCu lines can undergo localized melting and voiding under sub-critical current pulses that heat the lines well(More)
This paper demonstrates a new methodology for bringing accurate substrate resistance modeling into circuit level ESD simulation. The impact of layout and process variations on the effective substrate resistance of deep sub-micron ESD devices is analyzed and modeled using a quasi mixed-mode approach. The substrate resistance simulated by this method shows(More)
An adaptation strategy of CDR phase and ADC full scale range (FSR) for an ADC-based SerDes receiver is proposed and demonstrated in a 65-nm test chip. With the clock phase adapted by a metric based on the bit-error-rate (BER), the silicon operates over a wider range of channels or link settings compared to a typical Mueller-M&#x00FC;ller CDR algorithm. The(More)
This paper reports the use of a novel thermometry technique, scanning Joule expansion microscopy (SJEM), to study the steady state and dynamic thermal behavior of small geometry vias under sinusoidal and pulsed current stress for the first time. Spatial distribution of temperature rise surrounding a sub-micron via has been determined and the corresponding(More)
We are seeing a shift in electronic technology from centralized and high-touch to ubiquitous and low-touch. Semiconductors are enabling intelligent systems to be developed that enable a more immersive environment expanding the role and applications of electronic technology. Driving this change is the availability of low-power electronics for wireless(More)