Ajay kumar Dadoria

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As day by day continuing research in the field of nanotechnology, the CMOS manufacturing process scaled down in nano-dimensions at the cost of severe process variations and high leakage current which resulting large power dissipation. Therefore the leakage current and power dissipation becomes increasingly more focused in VLSI circuit design. Carbon(More)
Deep Sub Micron (DSM) technology demands for lower supply voltage, reduced threshold voltage and high transistor density which leads to exponentially increase in leakage power when circuit is in standby mode. To overcome from this situation Double Gate (DG) device like FinFET is used which have good control over the thin silicon fins with two tightly(More)
In this paper we presented a new 13T full adder design based on hybrid --CMOS logic design style. Adders are one of the most basic building blocks in digital components present in the Arithmetic Logic Unit (ALU). The performance of an adder have a significant impact on the overall performance of a digital system. The new design is compared with some(More)
Dynamic logic circuits are used for high performance and high speed applications. Wide OR gates are used in Dynamic RAMs, Static RAMs, high speed processors and other high speed circuits. In spite of their high performance, dynamic logic circuit has high noise and extensive leakage which has caused problems for the circuits. To overcome these problems(More)
Leakage power consumption is a major contribution of total power dissipation in Deep Sub-Micron (DSM) technology for CMOS circuit design. In this paper we have proposed a Novel circuit technique known as “Sleepy LECTOR” which mitigates various type of leakage current in DSM regime. In proposed technique we insert p-type sleep transistor above(More)
ABSTRACT This paper presents a design of a high speed Comparator design using 65nm digital CMOS technology on Cadence Virtuoso Design Tool. The proposed FLASH ADC Design consists of fully differential topology. The first stage provides a Voltage Divider circuit and the second stage is Comparator Design having high sampling frequency tolerance, and the high(More)
Low power designs has become one of the primary focus in Deep Sub-Micron (DSM) Technology. Optimization of speed, power and area can be achieved by using Gated Diffusion Input (GDI) technique. In this paper an 11T Adder using GDI technique is proposed and it is compared with various existing adder circuits for Average Power dissipation, delay & PDP.(More)
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