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1 This paper presents a test input data compression technique, which can be used to reduce input test data volume, test time, and the number of required tester channels. The technique is based on grouping data packets and applying various binary encoding techniques, such as Huffman codes and Golomb-Rice codes. Experiments on actual industrial designs and(More)
This paper describes a novel technique to selectively capture the scan fail data for volume diagnosis in the presence of output compression structures in a design. The proposed technique allows accurate fail data capture, at par with the uncompressed scan architectures, without reconfiguring the scan chains. The proposed technique uses the same test(More)
This paper presents a general economic modeling methodology for digital semiconductor production test approaches. The methodology can be used to quantify trade-offs and evaluate test approaches, including distributed test across test insertions, multi-site test, onchip/off-chip test trade-offs and ATE architectural tradeoffs, with modeled cost contributions(More)
The need for faster and more reliable yield ramp-up when introducing new CMOS technologies is driving the effort to acquire and analyze valuable information from production test, for the process of identification of yield detractors. This paper addresses a key step in the phase of "industrialization" of these processes: standardization. The objective of(More)