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Fabrication of high aspect ratio through silicon vias (TSVs) in a Si interposer and fine pitch solder microbumps on a top Si die is discussed in this paper. Chip stacking result of the Si interposer and the top Si die is also presented. TSVs with 25 μm in pitch and aspect ratio higher than 10 are etched with BOSCH process. To avoid difficulties in(More)
Developments of ultra fine pitch and high density solder microbumps for advanced 3D stacking technologies are discussed in this paper. CuSn solder microbumps with 25 ¿m in pitch are fabricated at wafer level by electroplating method and the total thicknesses of the platted Cu and Sn are 10 ¿m. After plating, the micro bumps on the Si chip are reflowed at(More)
High density three dimensional (3D) interconnects formed by high aspect ratio through silicon vias (TSVs) and fine pitch solder microbumps are presented in this paper. The aspect ratio of the TSV is larger than 10 and filled with Cu without voids; there are electrical nickel and immersion gold (ENIG) pads on top of the TSV as under bump metallurgy (UBM)(More)
In this paper, a reconfigurable filter using micromachined switches is designed, fabricated, and experimented. An equivalent-circuit model is derived for the reconfigurable cell structure. Extracted parameters show the characteristics of both bandpass and bandstop filters, which can be accurately analyzed using circuit analysis. Coplanar waveguide(More)
A new D2W collective bonding approach is demonstrated with functional MEMS devices with smaller than 3 &#x00D7; 3 mm<sup>2</sup> and 8 inch ASIC wafers. The new package design was proposed in order to reduce the parasitic effect by attaching the released MEMS dice directly to the pads on an ASIC wafer. Two different types of MEMS devices having combs(More)
Developments of ultra fine pitch and high density solder microbumps and assembly process for low cost 3D stacking technologies are discussed in this paper. The solder microbumps developed in this work consist of Cu and Sn, which are electroplated in sequential with total thickness of 10&#x00B5;m; The under bump metallurgy (UBM) pads used here is electroless(More)
In-based solders were chosen for the low temperature bonding at lower than 180degC. Three kinds of bonding types on Au/Cu/Ti/SiO<sub>2</sub>/Si dies, which were Sn/In and Au/In for Type 1, Au/In and Au/Sn for Type 2, and InSn alloy and InSn alloy for Type 3, were studied expecting that the whole In- solder layer is converted to the mixed intermetallic(More)
This paper presents micro fabrication process and wafer-level integration of a silicon carrier, which consists of two Si chips that are bonded together with evaporated AuSn-solder. There are micro fins and channels fabricated in the Si chip and form the embedded cooling layer after bonding. The embedded cooling layer is connected with an inlet and an outlet(More)
This paper presents micro fabrication process and wafer level integration of a silicon carrier, in which optimized liquid cooling layers are embedded. Two or more carriers can then be stacked together with a silicon interposer in between to make up of a stacked cooling module for high power heat dissipation. Wafer bonding are carried out with AuSn-solder(More)
This paper discusses wafer level vacuum sealing technology with evaporated AuSn solder for a microelectromechanical systems (MEMS) resonator without getter material. The MEMS resonator is fabricated and characterized in a vacuum chamber. Relationship between the Q-factor of the MEMS resonator and the vacuum level is established and used as a reference for(More)