Ahmet Ceyhan

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In this paper, we investigate the impact of local interconnect size effects on the performance of integrated circuits (ICs) based on timing-closed GDSII-level layouts of circuit blocks with detailed routing. For this purpose, we create multiple standard cell and interconnect libraries for 45-, 22-, 11-and 7-nm technology nodes considering scaling trends(More)
This paper presents the major limitations to the interconnect technology scaling at future technology generations and demonstrates both evolutionary and radical potential solutions to the BEOL scaling problem. To address the local interconnect challenges, a novel hybrid Al-Cu interconnect technology is introduced. Performances of carbon-based interconnects(More)
— Dimensional scaling of interconnects at future technology generations presents major limitations to the improvement of the performances of integrated circuits. In this paper, we investigate the impact of highly scaled Cu/low-κ interconnects on the speed and power dissipation of multiple circuit blocks based on timing-closed full-chip Graphic Database(More)
In this paper, emerging low-power interconnect options for CMOS and beyond CMOS technologies are reviewed. First, electrical interconnects based on carbon nanotubes and graphene nanoribbons are discussed. It is found that carbon-based electrical interconnects can potentially outperform their conventional Cu counterpart at technology nodes close to or below(More)
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