A fully integrated CMOS transceiver tuned to 2.1 GHz consumes 46 mA in receive-mode and 47 mA in transmit-mode from a 2.7 V supply. The receiver achieves a sensitivity of -80 dBm at 0.1% BER, and an IIP3 of -7 dBm. The transmitter delivers a GFSK modulated spectrum at an output power of 5 dBm.
— A 900-MHz direct-conversion receiver to detect a frequency-hopped carrier with frequency shift keying (FSK) modulation at 160 kb/s is integrated on the same chip as the transmitter. The receiver combines a low-noise amplifier with downconversion mixers and low-pass channel-select filters in quadrature channels. A digital correlating detector makes the… (More)
This paper presents integrated blocker filtering RF front-ends (BF-RF). In wireless cellular systems the blockers are from either self transmitters, such as WCDMA or form the other users' transmitters such as GSM. The proposed blocker filtering deploys the concept of blocker injection through feedforward or feedback paths to create arbitrary narrowband… (More)
A fully integrated system-on-a-chip intended for use in IEEE 802.11b applications is built in 0.18 /spl mu/m CMOS. All the radio building blocks, including the PA, the PLL loop filter, and the T/R switch, as well as the complete physical layer and the MAC sections, have been integrated into a single chip. The radio tuned to 2.4 GHz dissipates 165 mW in… (More)
A two-point modulation technique is presented that improves the performance of nonlinear power amplifiers (PAs) in polar transmitters. In this scheme, the output amplitude modulation is performed by controlling the current of the PA. The current control technique enables the PA to provide wideband amplitude modulation, as well as high power control dynamic… (More)
A novel switching power amplifier based on the concept of digital to analog converter (DAC) is presented for polar transmitter architecture. The novel idea in this amplifier is to generate a current proportional to the amplitude modulation signal and the power control bits. The current is then up-converted to the frequency of interest using switching… (More)
This paper presents a guideline to design and optimize a power harvester circuit for an RF identification transponder. A power harvester has been designed and fabricated in a CMOS 0.18- process that operates at the UHF band of 920 MHz. The circuit employs an impedance transformation circuit to boost the input RF signal that leads to the improvement of the… (More)
This paper presents an RF identification (RFID) system with a fully integrated transponder. To enable the on-chip integration of the tag's antenna, it is suggested to employ near-field coupling at high-frequency ranges, i.e., the UHF band. The RFID system including the reader and key blocks of the transponder is designed and fabricated in a standard CMOS… (More)