Afshin Seraj

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A linear delay element is proposed in 0.18 μm CMOS technology with a power supply of 1.8V. The proposed delay element maintains linearity over a relatively large input voltage range of 1.2V and its delay range (sensitivity) can be tuned through a bias voltage. Its power dissipation is 50μW at a clock frequency of 1GHz and its robustness in(More)
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