Adrian Maxim

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This paper describes a low-jitter phase-locked loop (PLL) implemented in a 0.18m CMOS process. A sample–reset loop filter architecture is used that averages the oscillator proportional control current which provides the feedforward zero over an entire update period and hence leads to a ripple-free control signal. The ripple-free control current eliminates(More)
  • Adrian Maxim
  • 2005 IEEE Radio Frequency integrated Circuits…
  • 2005
A 10 Gb/s limiting transimpedance amplifier was realized in a 0.2 μm SiGe technology having a 60 GHz transition frequency. A pseudo-differential common-emitter input stage with both capacitive and input bondwire inductive peaking was used to achieve high bandwidth and low noise performance. Cascode configurations and Miller capacitance(More)
A low noise and low spurs multi-GHz PLL frequency synthesizer was realized in a 0.13 μm CMOS process. A fully integrated loop filter was achieved by using a passive feedforward architecture that reduces the on-chip capacitance via a noiseless resistor multiplication. The reference spurs were minimized by using a fast switching charge-pump and a fast(More)
The first low-IF fully-integrated tuner for DBS satellite TV applications was realized in 0.13 mum CMOS. A wideband ring oscillator based frequency synthesizer having a large frequency step was used to down-convert a cluster of channels to a coarsely defined low-IF frequency, while the second down-conversion to baseband was performed in the digital domain.(More)
  • Adrian Maxim
  • 2005 IEEE Radio Frequency integrated Circuits…
  • 2005
A low phase noise multi-rate OC192 LC oscillator was realized in 0.13 μm CMOS. To minimize the gain of the oscillator, the frequency is first calibrated to within ±0.1% of the target value using a capacitor switching network and then the final locking is achieved with a PLL loop that controls a ±1% tuning range accumulation MOS(More)