Adrees Ahmad

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This paper presents two novel architectures for two-dimensional (2-D) Haar wavelet transform (HWT) of transform block in face recognition systems. The proposed architectures comprises 2-D HWT with transpose-based computation and dynamic partial reconfiguration (DPR) that have been synthesised using VHDL and implemented on Xilinx Virtex-5 FPGAs. To evaluate(More)
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