Adnan Kabbani

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In this paper, modified logical effort (MLE) technique is proposed to provide delay estimation for CMOS gates. The model accounts for the behavior of series-connected MOSFET structure (SCMS), the input transition time, and internodal charges. Also, the model takes into account deep submicron effects, such as mobility degradation and velocity saturation.(More)
  • Adnan Kabbani
  • 2008
This paper introduces a simple and yet accurate closed-form expression to estimate the switching power dissipation of static CMOS gates. The developed model depends on normalizing a gate- switching power to that of the unit standard inverter and it accounts for the effect of internodal capacitances. For different loads, gates and sizes, the developed model(More)
GAM, TPN and AWE methods have been accepted by many researchers as methods of modeling on-chip interconnects as RC, and RLC circuits. In this paper a platform to generate the T and Π configurations for RC, RLC and RLCG models based on GAM, TPN and AWE methods is proposed. With the Π configuration of AWE-based RLC model provides the best(More)
• Determined the optimum level of Intellectual Property (IP) blocks' development from re-usability and predictability point of view in Ultra Deep Submicron (UDSM) technology environment, as well as investigated the impact of target technology library-cells on the IP block design performance. • Developed technology-portable models to predict cell-timing(More)
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