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Category: B Intended for publication in the formal proceedings. All appropriate clearances for the publication of this paper have been obtained, and if accepted the author will prepare the final manuscript in time for inclusion in the Conference Proceedings and will present the paper at the conference. Summary VIS (Verification Interacting with Synthesis)… (More)
We present a logical formalism for expressing properties of continuous time Markov chains. The semantics for such properties arise as a natural extension of previous work on discrete time Markov chains to continuous time. The major result is that the veriication problem is decidable; this is shown using results in algebraic and transcendental number theory.
We present a logical formalism for expressing properties of continuous-time Markov chains. The semantics for such properties arise as a natural extension of previous work on discrete-time Markov chains to continuous time. The major result is that the verification problem is decidable; this is shown using results in algebraic and transcendental number theory.
In this paper the branching time logic pCTL is deened. pCTL expresses quantitative bounds on the probabilities of correct behavior ; it can be interpreted over discrete Markov processes. A bisim-ulation relation is deened on nite Markov processes, and shown to be sound and complete with respect to pCTL. We extend the universe of models to generalized Markov… (More)
During the muting of global interconnects, macro blocks form useful routing regions which allow wires to go through but forbid buffers to be inserted. They give restrictions on buffer locations. In this paper, we take these buffer location restrictions into consideration and solve the simultaneous maze routing and bufler insertion problem. Given a block… (More)
We address the problem of selecting repeater sizes and inserting at feasible locations in a placed and routed network to meet delay constraints using minimal repeater area, taking the advantage of slacks available in the network. Specifically, we transform the problem into an un-constrained optimization problem and solve it by iterative local refinement. We… (More)
The logic of equality with uninterpreted functions has been proposed for verifying abstract hardware designs. The ability to perform fast satissability checking over this logic is imperative for this veriication paradigm to be successful. We present symbolic methods for satissability checking for this logic. The rst procedure is based on restricting… (More)
We propose an integrated clock tree construction algorithm which performs simultaneous routing, wire sizing and buffer insertion. In existing approaches, wire sizing and clock buffer insertion are typically applied sequentially after a clock tree is generated and routed, i.e., they are done as post-processing steps. None of the known methods can perform… (More)
We present a simple and near optimal randomized parallel scheduling algorithm for scheduling packets in routers based on the <i>Switch-Memory-Switch</i> (<i>SMS</i>)architecture, which emulates 'output queuing' by using a collection of small memories within the switch to buffer packets, and which forms the basis of the fastest routers in use today. For a… (More)
We present an algorithm for simplifying the solution of conjunctive Boolean constraints of state and input variables, in the context of constrained random vector generation using BDDs. The basis of our approach is extraction of "hold-constraints" from constraint system. Hold-constraints are deterministic and trivially resolvable; in addition, they can be… (More)