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We present a logical formalism for expressing properties of continuous time Markov chains. The semantics for such properties arise as a natural extension of previous work on discrete time Markov chains to continuous time. The major result is that the veriication problem is decidable; this is shown using results in algebraic and transcendental number theory.

- Robert K. Brayton, Gary D. Hachtel, +13 authors Tiziano Villa
- CAV
- 1996

ion Manual abstraction can be performed by giving a file containing the names of variables to abstract. For each variable appearing in the file, a new primary input node is created to drive all the nodes that were previously driven by the variable. Abstracting a net effectively allows it to take any value in its range, at every clock cycle. Fair CTL model… (More)

- Adnan Aziz, Vigyan Singhal, Felice Balarin
- CAV
- 1995

In this paper the branching time logic pCTL is deened. pCTL expresses quantitative bounds on the probabilities of correct behavior ; it can be interpreted over discrete Markov processes. A bisim-ulation relation is deened on nite Markov processes, and shown to be sound and complete with respect to pCTL. We extend the universe of models to generalized Markov… (More)

- Adnan Aziz, Kumud Sanwal, Vigyan Singhal, Robert K. Brayton
- ACM Trans. Comput. Log.
- 2000

We present a logical formalism for expressing properties of continuous-time Markov chains. The semantics for such properties arise as a natural extension of previous work on discrete-time Markov chains to continuous time. The major result is that the verification problem is decidable; this is shown using results in algebraic and transcendental number theory.

- Anuj Goel, Khurram Sajid, Hai Zhou, Adnan Aziz, Vigyan Singhal
- CAV
- 1998

The logic of equality with uninterpreted functions has been proposed for verifying abstract hardware designs. The ability to perform fast satisfiability checking over this logic is imperative for such verification paradigms to be successful. We present symbolic methods for satisfiability checking for this logic. The first procedure is based on restricting… (More)

- Hai Zhou, Martin D. F. Wong, I-Min Liu, Adnan Aziz
- IEEE Trans. on CAD of Integrated Circuits and…
- 1999

During the muting of global interconnects, macro blocks form useful routing regions which allow wires to go through but forbid buffers to be inserted. They give restrictions on buffer locations. In this paper, we take these buffer location restrictions into consideration and solve the simultaneous maze routing and bufler insertion problem. Given a block… (More)

- Amit Prakash, Adnan Aziz, Vijaya Ramachandran
- INFOCOM
- 2004

We present new results and numerical studies of very fast schedulers for SMS (Switch-Memory-Switch) routers, which emulate output-queuing by buffering packets in a partitioned shared-memory located between input and output ports. The architecture of Juniper’s core routers and Brocade’s storage switches is based on SMS. Our numerical results demonstrate that… (More)

We address a problem of nding a nite state machine (FSM), which composed with a given FSM, satisses a given speciication. The composition we use is the standard synchronous automata composition restricted to cases which correctly model hardware interconnection. For the satisfaction relation, we use language containment. We present a procedure that will… (More)

- Shashank Gupta, Adnan Aziz
- Hot Interconnects
- 2002

We address the problem of serving multicast traffic in input-queued packet switches. Head-of-line blocking is a major problem in input-queued switches. It can be avoided in unicast switches by maintaining a queue per output port at each input port. This is not feasible in multicast switches, since the number of destination multicast addresses is exponential… (More)

- Eric Charles Quinnell, Jacob Abraham, +8 authors Marianne Quinnell
- 2007