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With increasing number of cores being integrated on a single die, Network-on-Chips (NoCs) have become the de-facto standard in providing scalable communication backbones for these multi-core chips. NoCs have a significant impact on the system's performance, power and reliability. However, NoCs can be plagued by higher power consumption and degraded(More)
Sub-threshold leakage in SRAM based cache memories is becoming a predominant source of power consumption in deep-sub micron CMOS designs. Phase Change Random Access Memory (PRAM), a high density, fast access, non-volatile memory is being considered as a candidate for future universal memory technologies. In this paper, we investigate the architectural(More)
The advent of diminutive technology feature sizes has led to escalating transistor densities. Burgeoning transistor counts are casting a dark shadow on modern chip design: global interconnect delays are dominating gate delays and affecting overall system performance. Networks-on-Chip (NoC) are viewed as a viable solution to this problem because of their(More)
We propose novel techniques to minimize the power and performance penalties in protecting the NoC against soft errors, while giving desired reliability guarantees. Some applications have inherent error tolerance which can be exploited to save power, by turning off the error correction mechanisms for a fraction of the total time without trading off(More)
The last few years have witnessed an unprecedented explosion in transistor densities. Diminutive feature sizes have enabled microprocessor designers to break the billion-transistors per chip mark. However various new reliability challenges such as process variation (PV) have emerged that can no longer be ignored by chip designers. In this paper, we provide(More)
Scratchpad memories (SPMs) have been shown to be more energy efficient and have faster access times than traditional hardware-managed caches. This, coupled with the predictability of data presence, makes SPMs an attractive alternative to cache for many scientific applications. In this work, we consider an SPM based system for increasing the performance and(More)
abStract Recently, chip multi-processors (CMP) have emerged to fully utilize the increased transistor count within stringent power budgets. Transistor scaling has lead to more error-prone and defective components. Static and run-time induced variations in the circuit lead to reduced yield and reliability. Providing reliability at low overheads specifically(More)
The gigahertz frequency regime together with the rising delay of on-chip interconnect and increased device densities , has resulted in aggravating clock skew problem. Skew and power dissipation of clock distribution networks are key factors in determining the maximum attainable clock frequency as well as the chip power consumption. The traditional skew(More)
The gigahertz frequency regime together with the rising delay of on-chip interconnect and increased device densities, has resulted in aggravating clock skew problem. Skew and power dissipation of clock distribution networks are key factors in determining the maximum attainable clock frequency as well as the chip power consumption. The traditional skew(More)
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