Adib Abrishamifar

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An efficient FPGA implementation of an irrational CIC filter for decimation in digital receivers is presented in this paper. The proposed approach employs dual-port RAMs prevailing in almost all recent FPGAs, favorably decreases the number of used slices and increases the operating frequency. The circuit has been implemented on a Xilinx Virtex-II Pro(More)
In this paper a new high speed and low power adder is presented. The circuit uses a hybrid concept of analog and digital circuit design to propagate the carry and so achieve a Full Adder with 78<sup>ps</sup> delay and 7.26<sup>&#x03BC;</sup><sup>w</sup> of power consumption. SPICE Simulations performed on the 0.18<sup>&#x03BC;m</sup> TSMC Technology(More)
This paper presents a single low-voltage CMOS analog multiplier with high-linearity, low total harmonic distortion and low-power consumption. It consists of four voltage adders, four nullors and a multiplier core. The proposed circuit is simulated with HSPICE and simulation results have shown that, under single 1V supply voltage, the circuit has smaller(More)
—Nowadays, multilevel voltage source inverters offer several advantages compared to their conventional two-level inverters. In these inverters, by synthesizing several levels of dc voltages, the staircase output waveform is produced. The structure of this waveform will have lower total harmonic distortion which leads to an approach to a desired sinusoidal(More)
In this paper, a control method is presented for induction motor which offers high efficiency and high dynamics even considering the influences of iron loss. Recently, research to consider the influences of iron loss has been made in the vector control of an induction motor. Vector control method is a quite complex task which demands precise information(More)