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Web-based instruction shows great promise toward enriching the student learning experience. One particular area of interest is providing tutorial material and practice problems online so that classroom lecture time can be better utilized. However, the time and cost to develop full tutoring systems can be prohibitive. The project presented in this paper(More)
As technology scaling increases embedded static random access memory bit-cell density, the number of soft errors due to radiation-induced multiple-bit upsets (MBUs) also increases. Traditionally, these errors have been addressed using a simple error correction code (ECC) combined with word interleaving. With continued scaling, however, errors beyond this(More)
Embedded memory is a critical component of modern SOCs. In highly scaled CMOS, process variability and device aging degradation cause a significant increase in the soft failure rate of embedded SRAMs. As process technology continues to scale, these issues become more pronounced, especially when the device is operating at its minimum operating voltage,(More)
With continuous and aggressive technology scaling, suppressing the stand-by power is among the top priorities for SRAM design. Switching off the less-frequently accessed blocks is an efficient way to reduce the stand-by power, provided that the information stored in these blocks can be restored. Non-volatile memories (NVMs) are integrated into SRAM cells to(More)
A 0.4 V single cycle 75 kbit SRAM macro protected with a multi-bit upset (MBU) correcting circuit is fabricated in a 28 nm LP-CMOS process. The novel error correcting circuit (ECC) is capable of 3-bit adjacent error correction and 8bit adjacent error detection. Simulation results show that the code provides a 2.35x improvement in corrected soft error rate(More)
We report on measured neutron radiation induced soft error rates (SER) for an academic, full-custom, low-power 75 kb SRAM macro in a commercial 28 nm CMOS process protected with an adjacent-bit error correction circuit (ECC). In low voltage (0.5 V) power saving mode, measurements show an 189x improvement in SER over an unprotected(More)
A 0.6 V low energy 64 kb SRAM-based PUF macro protected with a multi-bit error correcting circuit is fabricated in a 28 nm LP-CMOS process. The static noise margin difference (ΔSNM) is proposed as a design-time cell asymmetry metric for characterizing bitcell PUF response reproducibility. The ΔSNM is then used in conjunction with a Pelgrom's(More)
Interactive computer simulation tools are an essential component of a modern pedagogy for electrical and computer engineering. Simulation tools offer dynamic, interactive, self-paced learning that is available at the convenience of the student. At the University of Waterloo, Waterloo, ON, Canada, all senior level undergraduate students studying electrical(More)
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