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—Network-on-chip architectures can improve the scalability, performance, and power efficiency of general multi-processor systems and application-specific heterogeneous mul-ticore and many-core SoCs (MCSoCs). This interconnection paradigm when combined with 3D integration technology offers advantages over 2D NoC design, such as shorter wire length, higher(More)
Future high-performance embedded and general purpose processors and systems-on-chip are expected to combine hundreds of cores integrated together to satisfy the power and performance requirements of large complex applications. As the number of cores continues to increase, the employment of low-power and high-throughput on-chip interconnect fabrics becomes(More)
Photonic networks-on-chip (PNoCs) promise significant advantages over their electronic counterparts. In particular, they offer a potentially disruptive technology solution with fundamentally low power dissipation that remains independent of capacity while providing ultra-high throughput and minimal access latency. In conventional hybrid-PNoC systems,(More)
—In this paper, we present a low-cost deadlock-recovery technique for fault-tolerant routing algorithms in 3-dimensional Networks-on-Chip (3D-NoC) systems, called Random-Access-Buffer (RAB). RAB detects the presence of deadlock in the buffer and removes it with no considerable performance drop. The proposed deadlock-recovery technique was implemented on our(More)
—Recent technological advances in sensors, low-power microelectronics, and wireless networking enabled the proliferation of wireless sensor networks for wide applications. One of the promising applications of this domain is the distributed remote health monitoring of elderly people. An effective approach to speed up this and other bio-medical applications(More)
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