Abishek Manian

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— A 40-Gb/s equalizer incorporates a one-stage CTLE with 5.5-dB boost, a one-tap discrete-time linear equalizer with 5.4-dB boost, a two-tap half-rate/quarter-rate DFE, and charge-steering techniques. Realized in 45-nm CMOS technology, the equalizer achieves BER < 10 –12 with a clock phase margin of 0.28 UI with a channel loss of 20 dB at Nyquist. With the(More)
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