Reaching a power efficiency of 1mW/Gb/s has proven difficult for wireline transceivers operating at tens of gigabits per second. At 40Gb/s, recent receivers consume from 150mW  to 1W . This paper describes a receiver that achieves a tenfold reduction in power and an efficiency of 0.35mW/Gb/s. The proposed receiver uses a " minimalist " approach, which… (More)
— A 40-Gb/s equalizer incorporates a one-stage CTLE with 5.5-dB boost, a one-tap discrete-time linear equalizer with 5.4-dB boost, a two-tap half-rate/quarter-rate DFE, and charge-steering techniques. Realized in 45-nm CMOS technology, the equalizer achieves BER < 10 –12 with a clock phase margin of 0.28 UI with a channel loss of 20 dB at Nyquist. With the… (More)
A CTLE/DFE cascade incorporates inductor nesting to reduce chip area and latch feedforward to improve the loop speed. Realized in 45-nm CMOS technology, a 32-Gb/s prototype compensates for a channel loss of 18 dB at Nyquist while providing an eye opening of 0.44 UI at BER <; 10<sup>-12</sup>.