Abilio Parreira

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This paper presents a fault simulation algorithm that uses efficient partial reconfiguration of FPGAs. The methodology is particularly useful for evaluation of BIST effectiveness, and for applications in which multiple fault injection is mandatory, such as safety-critical applications. A novel fault collapsing methodology is proposed, which efficiently(More)
This paper addresses the problem of test quality assessment, namely of BIST solutions, implemented in FPGA and/or in ASIC, through Hardware Fault Emulation (HFE). A novel HFE methodology and tool is proposed, that, using partial reconfiguration, efficiently measures the quality of the BIST solution. The proposed HFE methodology uses Look-Up Tables (LUTs)(More)
This paper describes a new tool for Built in Self Test (BIST) design automation and fault emulation (FE). Combinational and/or sequential digital modules may be designed with embedded self-test attributes. Linear Feedback Shift Registers (LFSRs) and Multiple Input Shift Registers (MISRs) are automatically generated and connected to the circuit under test(More)
The purpose of this work is to present a Hardware Fault Simulation (HFS) methodology and tool (f 2 s), using partial reconfiguration, suitable for efficient fault modeling and simulation in FPGAs. The methodology is particularly useful for BIST effectiveness evaluation, and for applications in which multiple fault injection is mandatory, such as in(More)
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