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In this paper, we present Generic System Verilog Universal Verification Methodology based Reusable Verification Environment for efficient verification of Image Signal Processing IP's/SoC's. With the tight schedules on all projects it is important to have a strong verification methodology which contributes to First Silicon Success. Deploy methodologies which(More)
—With semiconductor industry trend of " smaller the better " , from an idea to a final product, more innovation on product portfolio and yet remaining competitive and profitable are few criteria which are culminating into pressure and need for more and more innovation for CAD flow, process management and project execution cycle. Project schedules are very(More)
In this paper we present the development of Acceleratable UVCs from standard UVCs in System Verilog and their usage in UVM based Verification Environment of Image Signal Processing designs to increase run time performance. This paper covers development of Acceleratable UVCs from standard UVCs for internal control and data buses of ST imaging group by(More)
Following the will to answer to the energy constrained applications requirements, an Ultra-Low Voltage (ULV) 40nm Bose-Chaudhuri-Hocquenghem (BCH) error-correcting circuit is presented. Mapped on a ULV specific standard cells library, the circuit was designed following standard industrial implementation and verification flows. The BCH circuit runs at(More)
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