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Comparison and Simulation of Analog and Digital Phase Locked Loop
TLDR
Final conclusion has been made between these two PLLs based on results observed and suitable areas of applications are suggested based on its performance. Expand
Design of Multi-PLL Board Using ARM7 Controller
TLDR
This paper presents the design of Multi-Phase Locked Loop (PLL) board which aims to provide different high frequency oscillator signals ranging from 960 MHz to 1.33 GHz to achieve stability at the output and the reduction of on-board interference thereby improving its usefulness in practical applications. Expand