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This paper investigates partitioning the ways of a shared last-level cache among the threads of a symmetric data-parallel application running on a chip-multiprocessor. Unlike prior work on way-partitioning for unrelated threads in a multiprogramming workload, the domain of multithreaded programs requires <i>both</i> throughput and fairness. Additionally,(More)
An increasing number of hardware failures can be attributed to device reliability problems that cause partial system failure or shutdown. In this paper we propose a scheme for improving reliability of a homogeneous chip multiprocessor (CMP) that also serves to improve manufacturing yield. Our solution centers on exploiting the natural redundancy that(More)
This paper outlines our ongoing efforts to effectively integrate a parallel file system in a cloud environment. We investigate how a parallel file system (PFS) can be effectively integrated and provided as a service to cloud users running High Performance Computing (HPC) applications, and what would be the performance and security implications of such a(More)
Multithreaded programs are commonly written and optimized for homogeneous multi-core processors assuming equal performance from all the cores. This assumption greatly simplifies the partitioning and balancing of an application's workload across threads; however, it no longer holds when the frequencies of the cores differ due to within-die variations,(More)
Task-parallel programming models with input annotation-based concurrency extraction at runtime present a promising paradigm for programming multicore processors. Through management of dependencies, task assignments, and orchestration, these models markedly simplify the programming effort for parallelization while exposing higher levels of concurrency. In(More)
A novel CDR system with a built-in equalizer for compensating electrical/optical channel loss is presented. A variable-gain delay line is implemented to perform both data delay and equalization simultaneously without consuming extra power. Designed in a 65-nm 1P9M general-purpose CMOS process, the proposed CDR system employs current-mode logic circuits(More)
Capacitive crosstalk induced signal integrity effects have been studied for over a decade. A typical victim net has multiple aggressors. In worst-case analysis of crosstalk effects, it is customary to assume that (i) all aggressors can switch at the same time and (ii) aggressors themselves are not subject to other crosstalk effects. Further refinements of(More)