Abhinav Kranti

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In this paper, gain-bandwidth (GB) trade-off associated with analog device/circuit design due to conflicting requirements for enhancing gain and cutoff frequency is examined. It is demonstrated that the use of a nonclassical source/drain (S/D) profile (also known as underlap channel) can alleviate the GB trade-off associated with analog design. Operational(More)
Most device simulation packages performing quantum transport modeling in thin body Multigate silicon nanowire devices at nanometer scales neglect the electron-phonon interaction, assuming devices operate in the ballistic regime. Here we perform a detailed study on dissipative quantum transport in multigate silicon nanowire transistor including acoustic and(More)
The work reports on the use of a planar tri-gate tunnel field effect transistor (TFET) to operate as dynamic memory at 85 °C with an enhanced sense margin (SM). Two symmetric gates (G1) aligned to the source at a partial region of intrinsic film result into better electrostatic control that regulates the read mechanism based on band-to-band tunneling, while(More)
The significance of optimization of gate–source/drain extension region (also known as underlap design) in double gate (DG) silicon-on-insulator (SOI) FETs to improve the linearity performance of a low power folded cascode operational transconductance amplifier (OTA) is described. Based on a new figure-of-merit (FoM) involving AV , linearity, fT and dc power(More)
In this paper we study the effect of emission and absorption processes due to inelastic optical phonons in multigate silicon nanowire transistors. We show that low-energy optical phonons reduce drain current through both phonon emission/absorption processes while high-energy phonons redistribute current spectrum inside the nanowire merely by phonon emission(More)
In the present work, we demonstrate the potential of double gate junctionless (JL) architecture for enhanced sensitivity for detecting biomolecules in cavity modulated field effect transistors (FETs). The higher values of body factor, achieved in asymmetric gate operation under impact ionization is utilized for enhanced sensing margin which is nearly five(More)
The paper investigates the impact of doping concentration on the performance of Ultra Low Power (ULP) Junctionless Double Gate MOSFETs. Results show that intrinsic delay is reduced by 69% and on-off current ratio is increased by 2.5 times when junctionless transistors are designed with a doping concentration of 5&#x00D7;10<sup>18</sup> cm<sup>-3</sup> as(More)