Abhinav Agarwal

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Using the example of a Reed–Solomon decoder, we provide insights into what type of hardware structures are needed to be generated to achieve specific performance targets. Due to the presence of run-time dependencies, sometimes it is not clear how the C code can be restructured so that a synthesis tool can infer the desired hardware structure. Such hardware(More)
This year’s MEMOCODE Design Contest challenged teams to implement the architecture for a unique type of Deep Packet Inspector called CANSCID. This type of architectural challenge represents a new direction for the contest, as previous years had focused on the acceleration of algorithmic specifications such as matrix multiplication. Despite such a(More)
In this paper, we propose the use of compressed sensing (CS) that is preceded by an energy-efficient, cross-product based independent component analysis (ICA) preprocessing method to efficiently compress electroencephalogram (EEG) signals in the context of a wireless body sensor network (WBSN). In WBSNs, the battery life puts a strict energy constraint at(More)
Whether for use as the final target or simply a rapid prototyping platform, programming systems containing FPGAs is challenging. Some of the difficulty is due to the difference between the models used to program hardware and software, but great effort is also required to coordinate the simultaneous execution of the application running on the microprocessor(More)
The emergence of data-intensive problems in areas like computational biology, astronomy, medical imaging, etc. has emphasized the need for fast and efficient very large Fourier Transforms. Recent work has shown that we can compute million-point transforms efficiently provided the data is sparse in the frequency domain. Processing input samples at rates(More)
Object tracking is fundamental to automated video surveillance, activity analysis and event recognition . In real-time applications only a small percentage of the system resources can be allocated for tracking, the rest being required for high-level tasks such as recognition, trajectory interpretation, and reasoning. There is a desperate need to carefully(More)
The diagram below shows the high level architecture of the Reed-Solomon decoder. It also indicates communication between modules using FIFOs. The blocks highlighted in orange are the primary modules of the algorithm, and are thus also the most complex. The primary modules receive t, and the error corrector received k from the iteration control module(More)
Using the example of a Reed-Solomon decoder, we provide insights into what type of hardware structures are needed to be generated to achieve specific performance targets. Due to the presence of run-time dependencies, sometimes it is not clear how the C code can be restructured so that a synthesis tool can infer the desired hardware structure. Such hardware(More)