Abhijith Arakali

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A supply-regulated phase-locked loop (PLL) employs a split-tuned architecture to decouple the tradeoff between supply-noise rejection performance and power consumption. The prototype PLL, incorporating a novel regulator, is fabricated in a 0.18 mum digital CMOS process and operates from 0.5 to 2.5 GHz. At 1.5 GHz, the proposed PLL achieves a worst-case(More)
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