Abdulmajid F. Al-Junaid

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The instruction set architecture (ISA) is the part of the processor that is visible to the programmer or compiler writer. Multi-level ISA is proposed to explicitly communicate data parallelism to hardware (processor) in a compact way instead of the dynamic extraction using complex hardware or the static extraction using sophisticated compiler techniques.(More)
Technological advances in IC manufacturing provide us with the capability to integrate more and more functionality into a single chip. Today's modern processors have nearly one billion transistors on a single chip. With the increasing complexity of today's system, the designs have to be modeled at a high-level of abstraction before partitioning into(More)
Discrete cosine transform (DCT) is one of the major operations in various image/video compression standards. This paper implements DCT and its inverse (IDCT) on our proposed Mat-Core processor using scalar/vector/matrix instruction sets. Mat-Core extends a general-purpose scalar processor with a matrix unit for processing vector/matrix data. The extended(More)
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