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Nanometer circuits are becoming increasingly susceptible to soft-errors due to alpha-particle and atmospheric neutron strikes as device scaling reduces node capacitances and supply/threshold voltage scaling reduces noise margins. It is becoming crucial to add soft-error tolerance estimation and optimization to the design flow to handle the increasing(More)
This paper proposes an optimum methodology forassigning supply and threshold voltages to modules in a CMOScircuit such that the overall energy consumption is minimizedfor a given delay constraint. The modules of the circuit shouldhave large enough gate depths such that the delay and energypenalties of the level shifters connecting them are negligible.Both(More)
Usage of dual supply voltages in a digital circuit is an effective way of reducing power consumption due to the quadratic relation of supply voltage to power consumption. But the need for level shifters when a low voltage gate drives a high voltage gate has been a limiting factor preventing widespread usage of dual supply voltages in digital circuit design.(More)
The continuous shrinking of microelectronic device sizes with every technology generation along with the reduction in supply voltages is causing a significant decrease in circuit noise margins. This leads to increased susceptibility of circuits to transient errors. In this paper, we propose a methodology to increase the robustness of combinational circuits(More)
Nanometer circuits are highly susceptible to soft errors generated by alpha-particle or atmospheric neutron strikes to circuit nodes. The reasons for the high susceptibility are the reduced node capacitances and noise margins caused by feature size and supply voltage scaling. Static soft error optimization (such as concurrent error detection or gate(More)
In this paper, a novel algorithm is proposed for assigning supply voltages to serially executing functional units (FUs) in a digital system such that the overall dynamic energy consumption is minimized for a given timing constraint. Novel closed form expressions for optimum supply voltage values are presented. The computation time of the algorithm is O(N)(More)
As technology scales to 40nm and beyond, intra-die process variability causes large delay and leakage variations across a chip in addition to expected die-to-die variations. In this paper, a new approach to post-manufacture circuit adaptation for yield maximization is proposed with special focus on the projected large intra-die variability of future CMOS(More)