Abdel Ejnioui

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Space applications rely increasingly on high data rate DSP algorithms. These algorithms use double precision floating point arithmetic operations. While most DSP applications can be compiled on DSP processors, high data rate DSP computations require novel implementation technologies to support their high throughputs. Only recently, gate densities in FPGAs(More)
The first step in high level synthesis consists of translating a behavioural specification into its corresponding register transfer language (RTL) description. Behavioural specifications are composed by writing code in a hardware description language such as VHDL. The process of translation starts by first deriving a control and data flow graph (CDFG) from(More)
The Tiered Algorithm is presented for time-efficient and message-efficient detection of process termination. It employs a global invariant of equality between process production and consumption at each level of process nesting to detect termination, regardless of execution interleaving order and network transit time. Correctness is validated for arbitrary(More)
Multi-FPGA systems are used as custom computing machines to solve compute intensive problems and also in the verification and prototyping of large circuits. In this paper, we address the problem of routing multi-terminal nets in a multi-FPGA system that uses partial crossbars as interconnect structures. First, we model the multi-terminal routing problem as(More)
In this paper, experiments are conducted in order to quantitatively evaluate the tradeoffs between design complexity and area overhead, reconfiguration flexibility, and reconfiguration latency of two reconfiguration interfaces, i.e. SelectMAP and JTAG. The results show that the SelectMAP interface is highly suitable when reconfiguration latency needs to be(More)
In this paper, we address the problem of routing nets on multi-FPGA systems interconnected by a switch matrix. Switch matrices were introduced to route signals going from one channel to another inside the FPGA chips. We extend the switch matrix architecture proposed by Zhu et al. [1] to route nets between FPGA chips in a multi-FPGA system. Given a limited(More)
Two different interfaces, namely the JTAG and SelectMAP interfaces, have been proposed for controlling and managing partial reconfiguration of SRAM-based Field Programmable Gate Arrays (FGPAs). Each of these interfaces provides distinct advantages in terms of area overhead and reconfiguration latency. In this paper, two corresponding sets of Application(More)
 Defragmentation is a fundamental resource management service allowing Reconfigurable Computing Systems (RCSs) to efficiently utilize resources when tasks are dispatched dynamically. Only well orchestrated interactions between the components of the reconfigurable resource management system can sustain the highest possible performance level for applications(More)