Aart J. de Geus

Learn More
This paper presents ESPRIT, an automatic test pattern generation (ATPG) system for testing single stuck-at faults in combinational logic. ESPRIT generates test patterns by performing fault simulation on random patterns derived from nonuniformly distributed input signal probabilities. The system computes input signal probabilities that minimize a testability(More)
This paper presents SOCRATES, a system of programs which synthesize and optimize combinational logic circuits from boolean equations. SOCRATES optimizes logic using boolean and algebraic minimization techniques, and it optimizes circuits derived from this logic in a user defined technology with a rule based expert system. This paper discusses the goals of(More)
The automation of the synthesis and optimization of combinational logic can result in savings in design time, significant improvements of the circuitry, and guarantee functional correctness. Synthesis quality is often measured in terms of the area of the circuit on the chip, which fails to take into account the timing constraints that might be imposed on(More)
Technology and Education Although Richard’s fascination with technology goes all the way back to his youth, it soared when he moved from the University of Melbourne to the University of California, Berkeley, in 1975. He immediately found an intellectual home in Don Pederson’s group, and the timing was fortunate. The Spice circuit simulator was spreading to(More)
Today's megatrends include: Consumer cycles at 6-12 months (and getting faster) Process technology accelerating through 45nm (but with higher risks and lower yields) Fewer platform SOCs (each requiring more specialized hardware and software design tools) The search for 3-4 more `waves' for the semiconductor industry to ride to $IT by the end of the CMOS(More)