Aaron Stillmaker

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— With deep submicron technology nodes other methods are needed to obtain scaling factors rather than the traditional scaling factors which held for the pre-submicron era. This work presents scaling factors between major technology nodes between 180 nm and 22 nm operating at voltages from 1.8 V to 0.7 V. Common operating data for these technologies were(More)
—Data centers require significant and growing amounts of power to operate, and with increasing numbers of data centers worldwide, power consumption for enterprise workloads is a significant concern. Sorting is a key computational kernel in large database systems, and the development of energy efficient sorting capabilities would therefore significantly(More)
—As processors move from multi-core to many-core architectures, opportunities arise for energy-efficient enterprise computations, such as sorting, on large arrays of processors. This paper proposes three different energy-efficient sorting methods for the first phase of an external sort simulated on a varying sized fine-grained many-core processor arrays(More)
1000 programmable processors and 12 independent memory modules capable of simultaneously servicing both data and instruction requests are integrated onto a 32nm PD-SOI CMOS device. At 1.1 V, processors operate up to an average of 1.78 GHz yielding a maximum total chip computation rate of 1.78 trillion instructions/sec. At 0.84 V, 1000 cores execute 1(More)
—The widths of data words in digital processors have a direct impact on area in application-specific ICs (ASICs) and FPGAs. Circuit area impacts energy dissipation per workload and chip cost. Floating-point exponent and mantissa widths are independently varied for the seven major computational blocks of an airborne synthetic aperture radar (SAR) engine. The(More)
This thesis describes the design and implementation of hardware and software which enable the integration of the 167-processor AsAP2 processor array chip into a system containing DRAM memory, mass storage, and high-speed interconnect. A new daughtercard utilizes high-speed LVDS interconnect for data and control interfaces between the array processor chip(More)
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