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Although carbon nanotube (CNT) transistors have been promoted for years as a replacement for silicon technology, there is limited theoretical work and no experimental reports on how nanotubes will perform at sub-10 nm channel lengths. In this manuscript, we demonstrate the first sub-10 nm CNT transistor, which is shown to outperform the best competing(More)
—Vertical single-walled carbon nanotubes (v-SWCNTs) are synthesized within highly ordered porous anodic alumina (PAA) templates supported on Si substrates. A process for obtaining thin-film PAA with long-range ordered nanopores is presented in this paper. Each nanopore contains at most one v-SWCNT that is supported by a dielectric and addressed by(More)
Moving beyond the limits of silicon transistors requires both a high-performance channel and high-quality electrical contacts. Carbon nanotubes provide high-performance channels below 10 nanometers, but as with silicon, the increase in contact resistance with decreasing size becomes a major performance roadblock. We report a single-walled carbon nanotube(More)
BACKGROUND: Transistors are one of the most enabling " hidden " technologies of all time and have facilitated the development of computers , the Internet, thin mobile displays, and much more. Silicon, which has been the material of choice for transistors in nearly every application for decades , is now reaching the fundamental limits to what it can offer(More)
The one-dimensional, cylindrical nature of single-walled carbon nanotubes ͑SWCNTs͒ suggests that the ideal gating geometry for nanotube field-effect transistors ͑FETs͒ is a surround gate ͑SG͒. Using vertical SWCNTs templated in porous anodic alumina, SGs are formed using top-down processes for the dielectric/metal depositions and definition of the channel(More)
  • Jieying Luo, Lan Wei, Chi-Shuen Lee, Aaron D Franklin, Ximeng Guan, Dimitri A Antoniadis +5 others
  • 2013
— A semianalytical carbon nanotube field-effect transistor (CNFET) model based on the virtual-source model is presented, which includes series resistance, parasitic capacitance, and direct source-to-drain tunneling leakage. The model is calibrated with recent experimental data down to 9-nm gate length. Device performance of 22-to 7-nm technology nodes is(More)
For more than 50 years, silicon transistors have been continuously shrunk to meet the projections of Moore's law but are now reaching fundamental limits on speed and power use. With these limits at hand, nanomaterials offer great promise for improving transistor performance and adding new applications through the coming decades. With different transistors(More)
—A carbon nanotube (CNT) thermometer that operates on the principles of electrical shot noise is reported. Shot noise thermometry is a self-calibrating measurement technique that relates statistical fluctuations in dc current across a device to temperature. A structure consisting of vertical, top, and bottom-contacted single-walled carbon nanotubes in a(More)
—A carbon nanotube (CNT) thermometer that operates on the principles of electrical shot noise is reported. Shot noise thermometry is a self-calibrating measurement technique that relates statistical fluctuations in dc current across a device to temperature. A structure consisting of vertical, top, and bottom-contacted single-walled carbon nanotubes in a(More)
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