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- Aamer Jaleel, Kevin B. Theobald, Simon C. Steely, Joel S. Emer
- ISCA
- 2010
Practical cache replacement policies attempt to emulate optimal replacement by predicting the re-reference interval of a cache block. The commonly used LRU replacement policy always predicts a… (More)
The commonly used LRU replacement policy is susceptible to thrashing for memory-intensive workloads that have a working set greater than the available cache size. For such applications, the majority… (More)
- David Wang, Brinda Ganesh, Nuengwong Tuaycharoen, Kathleen Baynes, Aamer Jaleel, Bruce Jacob
- SIGARCH Computer Architecture News
- 2005
As memory accesses become slower with respect to the processor and consume more power with increasing memory size, the focus of memory performance and power consumption has become increasingly… (More)
- Aamer Jaleel, William Hasenplaugh, Moinuddin K. Qureshi, Julien Sebot, Simon C. Steely, Joel S. Emer
- 2008 International Conference on Parallel…
- 2008
Chip Multiprocessors (CMPs) allow different applications to concurrently execute on a single chip. When applications with differing demands for memory compete for a shared cache, the conventional LRU… (More)
- Kenzo Van Craeynest, Aamer Jaleel, Lieven Eeckhout, Paolo Narváez, Joel S. Emer
- 2012 39th Annual International Symposium on…
- 2012
Single-ISA heterogeneous multi-core processors are typically composed of small (e.g., in-order) power-efficient cores and big (e.g., out-of-order) high-performance cores. The effectiveness of… (More)
- Carole-Jean Wu, Aamer Jaleel, William Hasenplaugh, Margaret Martonosi, Simon C. Steely, Joel S. Emer
- 2011 44th Annual IEEE/ACM International Symposium…
- 2011
The shared last-level caches in CMPs play an important role in improving application performance and reducing off-chip memory bandwidth requirements. In order to use LLCs more efficiently, recent… (More)
- Kursad Albayraktaroglu, Aamer Jaleel, +4 authors Donald Yeung
- IEEE International Symposium on Performance…
- 2005
Recent advances in bioinformatics and the significant increase in computational power available to researchers have made it possible to make better use of the vast amounts of genetic data that has… (More)
Chip multiprocessors are the next attractive point in the design space of future high performance processors. There is a growing need for simulation methodologies to determine the memory system… (More)
- Binh Hai Pham, Viswanathan Vaidyanathan, Aamer Jaleel, Abhishek Bhattacharjee
- 2012 45th Annual IEEE/ACM International Symposium…
- 2012
Translation Look aside Buffers (TLBs) are critical to system performance, particularly as applications demand larger working sets and with the adoption of virtualization. Architectural support for… (More)
- Aamer Jaleel, Eric Borch, Malini Bhandaru, Simon C. Steely, Joel S. Emer
- 2010 43rd Annual IEEE/ACM International Symposium…
- 2010
Inclusive caches are commonly used by processors to simplify cache coherence. However, the trade-off has been lower performance compared to non-inclusive and exclusive caches. Contrary to… (More)