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MIS: A Multiple-Level Logic Optimization System
TLDR
MIS is both an interactive and a batch-oriented multilevel logic synthesis and minimization system. Expand
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Storage assignment to decrease code size
TLDR
DSP architectures typically provide indirect addressing modes with autoincrement and decrement. Expand
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Performance-oriented technology mapping
TLDR
This thesis presents a variety of techniques to minimize circuit delay during the translation of a set of Boolean equations into a list of connected logic gates that can be used for the manufacturing of combinational digital circuits. Expand
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Storage assignment to decrease code size
TLDR
We present a formulation of the problem of optimal storage assignment such that explicit instructions for address arithmetic are minimized. Expand
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Multi-level logic minimization using implicit don't cares
TLDR
We introduce the concept of R-minimality, which implies minimality with respect to cube reshaping, and demonstrate the crucial role played by this concept in multilevel minimization. Expand
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Timing optimization of combinational logic
TLDR
An algorithm for speeding up combinational logic with minimal area increase is presented. Expand
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Computation of floating mode delay in combinational circuits: practice and implementation
TLDR
The authors use a recently developed single-vector condition, that is known to be necessary and sufficient for a path to be responsible for the delay of a circuit (i.e., true) in the floating delay model, to prove the truth or falsity of sets of paths in the circuit. Expand
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Certified timing verification and the transition delay of a logic circuit
The transition delay of a circuit is examined. It is shown that the transition delay of a circuit can differ from the floating delay even in the presence of arbitrary monotonic speedups in theExpand
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Code Optimization Techniques for Embedded DSP Microprocessors
TLDR
We address the problem of code optimization for embedded DSP microprocessors. Expand
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Algorithms for multilevel logic optimization
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