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A Scalable Architecture for Modular Multiplication Based on Montgomery's Algorithm
A word-based version of MM is presented and used to explain the main concepts in the hardware design and gives enough freedom to select the word size and the degree of parallelism to be used, according to the available area and/or desired performance.
A Scalable Architecture for Montgomery Multiplication
The general view of the new architecture is described, hardware organization for its parallel computation is analyzed, and design tradeoffs which are useful to identify the best hardware configuration are discussed.
A Scalable and Unified Multiplier Architecture for Finite Fields GF(p) and GF(2m)
A scalable and unified architecture for a Montgomery multiplication module which operates in both types of finite fields GF(p) and GF(2m) and utilizes the concurrency in the Montgomery multiplication operation by employing a pipelining design methodology.
High-Radix Design of a Scalable Modular Multiplier
This paper describes an algorithm and architecture based on an extension of a scalable radix-2 architecture proposed in a previous work. The algorithm is proven to be correct and the hardware design…
Multi-operand Floating-Point Addition
- A. Tenca
- Mathematics, Computer Science19th IEEE Symposium on Computer Arithmetic
- 8 June 2009
The design of a component to perform parallel addition of multiple floating-point (FP) operands is explored and the proposed design is more accurate than conventional FP addition using a network of 2-operand FP adders and it may have competitive area and delay depending on the number of input operands.
An efficient and scalable radix-4 modular multiplier design using recoding techniques
- A. Tenca, L. Tawalbeh
- Computer ScienceThe Thrity-Seventh Asilomar Conference on Signals…
- 9 November 2003
Experimental results are shown to demonstrate that the proposed Radix-4 Montgomery multiplier design has better area/performance tradeoff than previous radix-2 and 8 scalable designs.
A Parallel and Uniform $k$ -Partition Method for Montgomery Multiplication
- João Carlos Néto, A. Tenca, W. Ruggiero
- Computer Science, MathematicsIEEE Transactions on Computers
- 1 September 2014
A way to speed up the Montgomery Multiplication by distributing the multiplier operand bits into \mbi k partitions is proposed, showing that the hardware cost and its complexity have a linear growth according to the number of partitions.
New hardware algorithms and designs for montgomery modular inverse computation in galois fields gf(p) and gf(2n)
The computation of the inverse of a number in finite fields, namely Galois Fields GF(p) or GF(2n), is one of the most complex arithmetic operations in cryptographic applications. In this work, we…
Scalable and Unified Hardware to Compute Montgomery Inverse in GF(p) and GF(2)
A novel scalable and unified architecture for a Montgomery inverse hardware that operates in both GF(p) and GF(2n) fields is proposed, which allows the hardware to compute the inverse of long precision numbers in a repetitive way.
Multiplier architectures for GF(p) and GF(2n)
Two new hardware architectures are proposed for performing multiplication in GF(p) and GF (2/sup n/), which are the most time-consuming operations in many cryptographic applications. The…