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Correlation-aware statistical timing analysis with non-Gaussian delay distributions
Process variations have a growing impact on circuit performance for today's integrated circuit (IC) technologies. The non-Gaussian delay distributions as well as the correlations among delays makeExpand
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Model order-reduction of RC(L) interconnect including variational analysis
As interconnect feature sizes continue to scale to smaller dimensions, long interconnect can dominate the IC timing performance, but the interconnect parameter variations make it difficult to predictExpand
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Exploring regular fabrics to optimize the performance-cost trade-off
While advances in semiconductor technologies have pushed achievable scale and performance to phenomenal limits for ICs, nanoscale physical realities dictate IC production based on what we can afford.Expand
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Projection-based performance modeling for inter/intra-die variations
Large-scale process fluctuations in nano-scale IC technologies suggest applying high-order (e.g., quadratic) response surface models to capture the circuit performance variations. Fitting such modelsExpand
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Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings
The financial backbone of the semiconductor industry is based on doubling the functional density of integrated circuits every two years at fixed wafer costs and die yields. The increasing demands forExpand
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Statistical critical path analysis considering correlations
Critical path analysis is always an important task in timing verification. For todays nanometer IC technologies, process variations have a significant impact on circuit performance. The variabilityExpand
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Impact of interconnect variations on the clock skew of a gigahertz microprocessor
Due to the large die sizes and tight relative clock skew margins, the impact of interconnect manufacturing variations on the clock skew in today's gigahertz microprocessors can no longer be ignored.Expand
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VLSI Yield Prediction and Estimation: A Unified Framework
In this paper we present a unified framework for prediction and estimation of the manufacturing yield of VLSI circuits. We formally introduce a number of yield measures that are useful both duringExpand
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A Methodology for Worst-Case Analysis of Integrated Circuits
Worst-case analysis is one of the most often used techniques for verifying that the sensitivity of integrated circuit (IC) performances to changes in manufacturing conditions is minimized. However,Expand
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Design methodology for IC manufacturability based on regular logic-bricks
Implementing logic blocks in an integrated circuit in terms of repeating or regular geometry patterns (Palusinski et al., 2001 and Strojwas, 2003) can provide significant advantages in terms ofExpand
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