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Analysis and compact modeling of lateral DMOS power devices under ESD stress conditions
The detailed physical mechanisms specific to 40 V LDMOS power transistors under ESD stress (gate grounded/coupled) are investigated by means of TLP measurements/HBM testing, electron emissionExpand
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Surface mobility in silicon at large operating temperature
An experimental investigation on high-temperature carrier mobility in silicon inversion layers is carried out with the aim of improving our understanding of carrier transport at the onset of secondExpand
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Layout optimization of an ESD-protection n-MOSFET by simulation and measurement
This paper presents a new method for optimizing the performance of a lateral npn-transistor used as ESD protection element. Relying on process modeling and thermo-electrical device simulations we areExpand
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Process variability analysis of a Si/SiGe HBT technology with greater than 200 GHz performance
A process tolerance analysis of a SiGe NPN HBT with >200 GHz f/sub T/ and >250 GHz f/sub MAX/ is presented. AC and DC device results on 200 mm wafers demonstrate a wide process window resulting in aExpand
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A versatile setup for semiconductor testing up to 550/spl deg/C
We describe a novel setup designed for measuring semiconductor devices at temperatures up to 550/spl deg/C and report on some promising early measurements of a 1 /spl mu/m MOSFET in the range fromExpand
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Biodegradable Block Copolymers, Star-Shaped Polymers, and Networks Via Ring-Expansion Polymerization
Over the past decades biodegradable (or more precisely “resorbable”) polyesters have found rapidly increasing interest of scientists and chemical companies. Among the numerous potential applicationsExpand