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Power LDMOS with novel STI profile for improved Rsp, BVdss, and reliability
The profile of shallow trench isolation (STI) is designed to improve LDMOS specific on-resistance (Rsp), BVDSS, safe operating area (SOA), and hot carrier lifetimes (HCL) in an integrated BiCMOS
Improving the ESD self-protection capability of integrated power NLDMOS arrays
The self-protection capability (SPC) of integrated power arrays in ESD regimes has been studied for the case of integrated 100 V NLDMOS arrays in a BCD process. A new practical methodology for array
Optimization of LDMOS array design for SOA and hot carrier lifetime
TLDR
This work focuses on novel results in the use of layout techniques and cell design to improve both SOA and hot carrier reliability of LDMOS arrays.
Hot carrier reliability of N-LDMOS transistor arrays for power BiCMOS applications
This paper evaluates the hot carrier performance of n-channel lateral DMOS (N-LDMOS) transistors. The N-LDMOS has been the common choice for the driver transistor in high voltage (20-30 V) smart
A trench-isolated power BiCMOS process with complementary high performance vertical bipolars
A new process for mixed-signal and power management applications is introduced. The process architecture is designed to achieve high V/sub A/, high f/sub T/ complementary 24 V bipolar devices coupled
Monolithic integration of trench vertical DMOS (VDMOS) power transistors into a BCD process
The monolithic integration of trench vertical DMOS (VDMOS) n-channel transistors into an IC BCD process is reported for the first time. The integration scheme for the trench VDMOS module is discussed
PMOS drain breakdown voltage walk-in: a new failure mode in high power BiCMOS applications
High voltage power management applications often require 50V to 100V operation. These circuits are implemented in a BiCMOS processes and support both low voltage (5-15V) and high voltage devices. In
Design optimization of N-LDMOS transistor arrays for hot carrier lifetime enhancement
Today's power management devices often require operation in the 20-30 V range. These applications combine a high performance BiCMOS process with a power lateral n-channel DMOS (N-LDMOS) driver. To
1-D and 2-D hot carrier layout optimization of N-LDMOS transistor arrays
Today's power management devices often require operation in the 20-30 V range. These applications often combine a high performance BiCMOS process with a power lateral DMOS (LDMOS) driver. To obtain
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