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A novel mixed-signal digital CMOS fuzzy logic controller in current mode
This article discusses about a fuzzy controller. The fuzzifier is designed with a novel structure which is more suitable than other topologies and it has a high accuracy and speed. The processingExpand
  • 7
Digitally-assisted gain calibration strategy for open-loop residue amplifiers in pipeline ADCs
  • S. Kazeminia, A. Soltani
  • Mathematics, Computer Science
  • IEEE Asia Pacific Conference on Circuits and…
  • 1 October 2016
TLDR
A digitally-assisted foreground-liked gain calibration mechanism is proposed for open loop residue amplifiers that resolves discontinuous conversion in regular foreground methods. Expand
  • 1
An Ultra High speed Low power Low settling time error and wide dynamic range voltage Continuous-time Common-Mode Feedback Circuit in 0.18µm CMOS
TLDR
A novel method to design continuous-time common-mode feedback circuit is presented in this paper. Expand
  • 4
Fast and accurate fractional frequency synthesizer in 0.18μm technology
A 900MHz frequency synthesizer is presented in this article. The purpose of the proposed architecture is to minimize lock time in Phase-Locked Loops (PLLs). The structure has been simulated by HSPICEExpand
  • 2
A new ultra high speed 7-2 compressor with a new structure
TLDR
This paper devotes to a 7-2 compressor designed according to a new architecture with a pure Glitchless output. Expand
  • 1
A 6-bit 800MS/s flash ADC in 0.35μm CMOS
TLDR
In this work, a 6-bit 800 MS/s flash analog-to-digital converter (ADC) is proposed. Expand
  • 2
In-Vivo Optical Strain Measurements of the Human Heart
Digital image correlation is a suitable method for motion and deformation measurements especially in such cases where physical contact with the measured object is limited. In our previous researchExpand
Programmable incrementing/decrementing binary accumulator for high-speed calibration loops
TLDR
In this paper a structure for high-speed incrementing/decrementing accumulator is proposed based on even and odd unit cells. Expand
Single-stage offset-cancelled latched comparator scheduled by multi-level control on reset switch
  • S. Kazeminia, A. Soltani
  • Engineering, Computer Science
  • IEEE Asia Pacific Conference on Circuits and…
  • 1 October 2016
TLDR
A single-stage hardware is scheduled for multiple operations, reset, offset cancellation, pre-amplification and latch. Expand