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An OpenCL™ Deep Learning Accelerator on Arria 10
TLDR
We show a novel architecture written in OpenCL(TM), which we refer to as a Deep Learning Accelerator (DLA), that maximizes data reuse and minimizes external memory bandwidth. Expand
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An OpenCL(TM) Deep Learning Accelerator on Arria 10
TLDR
We show a novel architecture written in OpenCL(TM), which we refer to as a Deep Learning Accelerator (DLA), that maximizes data reuse and minimizes external memory bandwidth to significantly boost the performance of FPGA. Expand
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FPGA technology mapping: a study of optimality
TLDR
This paper attempts to quantify the optimality of FPGA technology mapping algorithms. Expand
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Characterization and clinical course of 1000 patients with coronavirus disease 2019 in New York: retrospective case series
Abstract Objective To characterize patients with coronavirus disease 2019 (covid-19) in a large New York City medical center and describe their clinical course across the emergency department,Expand
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Characterization and clinical course of 1000 patients with COVID-19 in New York: retrospective case series
Objective: To characterize patients with coronavirus disease 2019 (COVID-19) in a large New York City (NYC) medical center and describe their clinical course across the emergency department (ED),Expand
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Towards scalable placement for FPGAs
TLDR
In this paper, we attempt to make a rigorous comparison of a recent crop of academic ASIC placers and VPR when applied to modern FPGA device features and design sizes. Expand
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DLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration
TLDR
In this paper, we tailor an overlay to a specific application domain, and we show how we maintain its full programmability without paying for the performance overhead traditionally associated with overlays. Expand
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Harnessing the power of FPGAs using altera's OpenCL compiler
TLDR
In recent years, Field-Programmable Gate Arrays have become extremely powerful computational platforms that can efficiently solve many complex problems. Expand
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Toward Automated ECOs in FPGAs
TLDR
This paper introduces a novel resynthesis technique which can automatically update the functionality of a circuit by leveraging the existing logic within the design, thereby removing the inefficient manual effort required by a designer. Expand
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In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC
TLDR
We propose TensorTile ASICs for Stratix10 FPGAs to provide ASIC-level tensor performance, while relying on FPGA's flexibility for application-specific operations. Expand
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