A. Ling

Publications
Influence

An OpenCL™ Deep Learning Accelerator on Arria 10

U. Aydonat, S. O'Connell, D. Capalija, A. Ling, Gordon R. Chiu
Computer Science
FPGA
13 January 2017

We show a novel architecture written in OpenCL(TM), which we refer to as a Deep Learning Accelerator (DLA), that maximizes data reuse and minimizes external memory bandwidth. Expand

An OpenCL(TM) Deep Learning Accelerator on Arria 10

U. Aydonat, S. O'Connell, D. Capalija, A. Ling, Gordon R. Chiu
Computer Science
13 January 2017

We show a novel architecture written in OpenCL(TM), which we refer to as a Deep Learning Accelerator (DLA), that maximizes data reuse and minimizes external memory bandwidth to significantly boost the performance of FPGA. Expand

FPGA technology mapping: a study of optimality

A. Ling, D. Singh, S. Brown
Computer Science
Proceedings. 42nd Design Automation Conference, .
13 June 2005

This paper attempts to quantify the optimality of FPGA technology mapping algorithms. Expand

Characterization and clinical course of 1000 patients with coronavirus disease 2019 in New York: retrospective case series

M. Argenziano, Samuel L Bruce, +45 authors R. Chen
Medicine
BMJ
29 May 2020

Abstract Objective To characterize patients with coronavirus disease 2019 (covid-19) in a large New York City medical center and describe their clinical course across the emergency department,… Expand

Characterization and clinical course of 1000 patients with COVID-19 in New York: retrospective case series

M. Argenziano, Samuel L Bruce, +45 authors R. Chen
Medicine
medRxiv
22 April 2020

Objective: To characterize patients with coronavirus disease 2019 (COVID-19) in a large New York City (NYC) medical center and describe their clinical course across the emergency department (ED),… Expand

Towards scalable placement for FPGAs

H. Bian, A. Ling, Alexander Choong, J. Zhu
Computer Science
FPGA '10
21 February 2010

In this paper, we attempt to make a rigorous comparison of a recent crop of academic ASIC placers and VPR when applied to modern FPGA device features and design sizes. Expand

DLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration

M. Abdelfattah, David Han, +8 authors Gordon R. Chiu
Computer Science, Engineering
28th International Conference on Field…
13 July 2018

In this paper, we tailor an overlay to a specific application domain, and we show how we maintain its full programmability without paying for the performance overhead traditionally associated with overlays. Expand

Harnessing the power of FPGAs using altera's OpenCL compiler

D. Singh, T. Czajkowski, A. Ling
Computer Science
FPGA '13
11 February 2013

In recent years, Field-Programmable Gate Arrays have become extremely powerful computational platforms that can efficiently solve many complex problems. Expand

Toward Automated ECOs in FPGAs

A. Ling, S. Brown, J. Zhu, Sean Safarpour
Computer Science
IEEE Transactions on Computer-Aided Design of…
24 February 2009

This paper introduces a novel resynthesis technique which can automatically update the functionality of a circuit by leveraging the existing logic within the design, thereby removing the inefficient manual effort required by a designer. Expand

In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC

Eriko Nurvitadhi, J. Cook, +8 authors A. Dasu
Computer Science
28th International Conference on Field…
15 February 2018

We propose TensorTile ASICs for Stratix10 FPGAs to provide ASIC-level tensor performance, while relying on FPGA's flexibility for application-specific operations. Expand

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