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Lock reservation: Java locks can mostly do without atomic operations
TLDR
This paper presents a novel algorithm called lock reservation, which exploits thread locality of Java locks, which claims that the locking sequence of a Java lock contains a very long repetition of a specific thread. Expand
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Lock Reservation for Java Reconsidered
TLDR
Lock reservation, a powerful optimization for Java locks, is based on the observation that, in Java, each lock tends to be dominantly acquired and released by a specific thread. Expand
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Evolution of a Java just-in-time compiler for IA-32 platforms
TLDR
This paper describes the design and implementation of our JIT compiler for IA-32 platforms by focusing on the recent advances achieved in the past several years. Expand
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Effectiveness of cross-platform optimizations for a java just-in-time compiler
TLDR
This paper describes the system overview of our Java Just-In-Time (JIT) compiler, which is the basis for the latest production version of IBM Java JIT compiler that supports a diversity of processor architectures including both 32-bit and 64-bit modes, CISC, RISC, and VLIW architectures. Expand
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A method for estimating optimal unrolling times for nested loops
TLDR
This paper describes a heuristic algorithm for deciding the number of times and the directions in which loops should be unrolled, through the use of information such as dependence, reuse, and machine resources. Expand
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Preference-directed graph coloring
TLDR
This paper describes a new framework of register allocation based on Chaitin-style coloring based on a graph representation of preferences called a Register Preference Graph, which helps find a good register selection. Expand
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Effectiveness of cross-platform optimizations for a java just-in-time compiler
TLDR
This paper describes the system overview of our Java Just-In-Time (JIT) compiler, which is the basis for the latest production version of IBM Java JIT compiler that supports a diversity of processor architectures including both 32-bit and 64-bit modes, CISC, RISC, and VLIW architectures. Expand
  • 16
Spill code minimization by spill code motion
TLDR
We propose a new technique for partial spilling called spill code motion. Expand
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A register allocation technique using guarded PDG
TLDR
Register allocation for instruction-level parallel processors involves problems that are not considered in register allocat,i on for scalar processors. Expand
  • 3
Distributed and fault-tolerant execution framework for transaction processing
TLDR
This paper presents a new fault tolerant execution framework that addresses both of these requirements. Expand
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