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Silicon-photonic clos networks for global on-chip communication
TLDR
Analytical modeling is used to show that a 64-tile photonic Clos network consumes significantly less optical power, thermal tuning power, and area compared to global photonic crossbars over a range of photonic device parameters. Expand
Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics
We present a new monolithic silicon photonics technology suited for integration with standard bulk CMOS processes, which reduces costs and improves opto-electrical coupling compared to previousExpand
Analysis of redundancy and application balance in the SPEC CPU2006 benchmark suite
TLDR
This paper analyzes the SPEC CPU2006 benchmarks using performance counter based experimentation from several state of the art systems, and uses statistical techniques such as principal component analysis and clustering to draw inferences on the similarity of the benchmarks and the redundancy in the suite and arrive at meaningful subsets. Expand
Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics
TLDR
A new monolithic silicon-photonic technology is introduced, which uses a standard bulk CMOS process to reduce costs and improve energy efficiency, and the logical and physical implications of leveraging this technology in processor-to-memory networks are explored. Expand
Measuring benchmark similarity using inherent program characteristics
TLDR
From the study of the similarity between the four generations of SPEC CPU benchmark suites, it is found that, other than a dramatic increase in the dynamic instruction count and increasingly poor temporal data locality, the inherent program characteristics have more or less remained unchanged. Expand
Measuring Program Similarity: Experiments with SPEC CPU Benchmark Suites
TLDR
This paper applies their methodology to the SPEC CPU2000 benchmark suite and demonstrates that a subset of 8 programs can be used to effectively represent the entire suite, and proves the usefulness of this subset by using it to estimate the average IPC and L1 data cache miss-rate of the entire suites. Expand
Re-architecting DRAM memory systems with monolithically integrated silicon photonics
TLDR
This work redesigns the DRAM main memory system using a proposed monolithically integrated silicon photonics technology and shows that the photonically interconnected DRAM (PIDRAM) provides a promising solution to all of these issues. Expand
Designing Chip-Level Nanophotonic Interconnection Networks
TLDR
This paper uses the ongoing work on leveraging nanophotonics in an on-chip title-to-tile network, processor- to-main-memory network, and dynamic random-access memory (DRAM) channel to illustrate this design process. Expand
Automated microprocessor stressmark generation
TLDR
This paper demonstrates that with a suitable choice of only 40 hardware-independent program characteristics related to the instruction mix, instruction-level parallelism, control flow behavior, and memory access patterns, it is possible to generate a synthetic benchmark whose performance relates to that of general-purpose and commercial applications. Expand
Thermal management of manycore systems with silicon-photonic networks
TLDR
A novel job allocation technique is introduced that minimizes the temperature gradients among the ring modulators/filters to improve the application performance and compared to existing workload allocation policies, the proposed policy improves system performance. Expand
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