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Silicon-photonic clos networks for global on-chip communication

Analytical modeling is used to show that a 64-tile photonic Clos network consumes significantly less optical power, thermal tuning power, and area compared to global photonic crossbars over a range of photonic device parameters.
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Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics

We present a new monolithic silicon photonics technology suited for integration with standard bulk CMOS processes, which reduces costs and improves opto-electrical coupling compared to previous…
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Analysis of redundancy and application balance in the SPEC CPU2006 benchmark suite

This paper analyzes the SPEC CPU2006 benchmarks using performance counter based experimentation from several state of the art systems, and uses statistical techniques such as principal component analysis and clustering to draw inferences on the similarity of the benchmarks and the redundancy in the suite and arrive at meaningful subsets.
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Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics

A new monolithic silicon-photonic technology is introduced, which uses a standard bulk CMOS process to reduce costs and improve energy efficiency, and the logical and physical implications of leveraging this technology in processor-to-memory networks are explored.
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Measuring benchmark similarity using inherent program characteristics

From the study of the similarity between the four generations of SPEC CPU benchmark suites, it is found that, other than a dramatic increase in the dynamic instruction count and increasingly poor temporal data locality, the inherent program characteristics have more or less remained unchanged.
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Designing Chip-Level Nanophotonic Interconnection Networks

This paper uses the ongoing work on leveraging nanophotonics in an on-chip title-to-tile network, processor- to-main-memory network, and dynamic random-access memory (DRAM) channel to illustrate this design process.
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Re-architecting DRAM memory systems with monolithically integrated silicon photonics

This work redesigns the DRAM main memory system using a proposed monolithically integrated silicon photonics technology and shows that the photonically interconnected DRAM (PIDRAM) provides a promising solution to all of these issues.
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Performance Cloning: A Technique for Disseminating Proprietary Applications as Benchmarks

A technique that can automatically extract key performance attributes of a real world application and clone them into a synthetic benchmark, where the performance and power consumption correlates well with that of the original application across a wide range of microarchitecture configurations.
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Asymmetric NoC Architectures for GPU Systems

An asymmetric NoC design tailored for a GPU's memory access pattern is explored, providing one network for L1-to-L2 communication and a second for L2- to-L1 traffic, showing that an asymmetric multi-network Cmesh provides the most energy-efficient communication fabric for the target GPU system.
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Hardware Performance Counters Can Detect Malware: Myth or Fact?

It is claimed and experimentally support that using the micro-architectural level information obtained from HPCs cannot distinguish between benignware and malware, and it is shown that one benignware infused with malware cannot be detected by HPC-based malware detection.
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