• Publications
  • Influence
The ATLAS Collaboration
The simulation software for the ATLAS Experiment at the Large Hadron Collider is being used for large-scale production of events on the LHC Computing Grid. This simulation requires many components,Expand
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A network on chip architecture and design methodology
TLDR
We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. Expand
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Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip
TLDR
In today's emerging network-on-chips, there is a need for different traffic classes with different quality-of-service guarantees. Expand
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Run-time Partial Reconfiguration speed investigation and architectural design space exploration
TLDR
In this paper, we propose to use Direct Memory Access (DMA), Master (MST) burst, and a dedicated Block RAM (BRAM) cache respectively to reduce the reconfiguration time by one order of magnitude, with little resource consumption overhead. Expand
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Methods for fault tolerance in networks-on-chip
TLDR
Research on fault-tolerant Networks-on-Chip tries to mitigate partial failure and its effect on network performance and reliability by exploiting various forms of redundancy at the suitable network layers. Expand
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Networks on chip
TLDR
We are witnessing a growing interest in Networks on Chips (NoC) that is related to the evolution of integrated circuit technology and to the growing requirements in performance and portability of electronic systems. Expand
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Network on Chip : An architecture for billion transistor era
TLDR
This paper presents Network on a chip (NOC) concept and its associated methodology as solu the design productivity problem. Expand
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Modeling embedded systems and SoCs - concurrency and time in models of computation
  • A. Jantsch
  • Computer Science
  • The Morgan Kaufmann series in systems on silicon
  • 17 June 2003
Preface 1. Introduction 2. Behavior and Concurrency 3. The Untimed Model of Computation 4. The Synchronous Model of Computation 5. The Timed Model of Computation 6. MoC Interfaces 7. Tightly CoupledExpand
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An Analytical Latency Model for Networks-on-Chip
TLDR
We propose an analytical model based on queueing theory for delay analysis in a wormhole-switched network-on-chip. Expand
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The Nostrum backbone-a communication protocol stack for Networks on Chip
TLDR
We propose a communication protocol stack to be used in Nostrum, our Network on Chip (NoC) architecture. Expand
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