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A 14nm logic technology using 2<sup>nd</sup>-generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical patterning layers, and air-gapped(More)
We have found that the room-temperature 1/<i>f</i>-noise gate-voltage and frequency dependences of pMOS transistors are affected significantly by moisture exposure and total dose irradiation. The(More)