A. Das

We present a survey on the state-of-the-art in scan-based side-channel attacks on symmetric and public-key cryptographic hardware implementations, both in the absence and presence of advanced DfT structures. Expand

In this paper we propose a novel architecture that implements a secure JTAG interface. Expand

We show the actual power consumption graphs of those operations on a FPGA platform and propose a modified arithmetic and its suitable implementation technique. Expand

This article focuses on detecting attacks to power system with the help of cyber-physical co-modeling. Expand

We demonstrate how power management vulnerabilities can enable covert communication over a previously unexplored, novel class of covert channels which we refer to as POWERT channels. Expand

We enhance the secure test wrapper allowing testing of multiple IP blocks using a PUF-based authentication mechanism which overcomes the necessity of secure NVM and reduces the implementation overhead. Expand

We propose a secure challenge-response based Secure Test Wrapper structure, suitable for testing IP cores in a SoC environment, which provides full testability, very high security and scalability of the proposed design. Expand

This paper presents a performance comparison of new authenticated encryption (AE) algorithms which are aimed at providing better security and resource efficiency compared to existing standards. Expand

We perform a comprehensive area, power, and energy analysis of some of the most recently-developed lightweight block ciphers and we compare them to the standard AES algorithm. Expand