Share This Author
DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling
- Chen Sun, C. Chen, V. Stojanović
- Physics, Computer ScienceIEEE/ACM Sixth International Symposium on…
- 9 May 2012
DSENT, a NoC modeling tool for rapid design space exploration of electrical and opto-electrical networks, is presented and the results show the implications of different technology scenarios and the need to reduce laser and thermal tuning power in a photonic network due to their non-data-dependent nature.
On-Chip Interconnection Architecture of the Tile Processor
IMesh, the tile processor architecture's on-chip interconnection network, connects the multicore processor's tiles with five 2D mesh networks, each specialized for a different use. taking advantage…
Graphite: A distributed parallel simulator for multicores
- Jason E. Miller, H. Kasture, A. Agarwal
- Computer ScienceHPCA - 16 The Sixteenth International Symposium…
- 1 April 2010
This paper introduces the Graphite open-source distributed parallel multicore simulator infrastructure and demonstrates that Graphite can simulate target architectures containing over 1000 cores on ten 8-core servers with near linear speedup.
The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs
The Raw microprocessor research prototype uses a scalable instruction set architecture to attack the emerging wire-delay problem by providing a parallel, software interface to the gate, wire and pin resources of the chip.
Limits on Interconnection Network Performance
- A. Agarwal
- Computer ScienceIEEE Trans. Parallel Distributed Syst.
- 1 October 1991
A simple closed-form expression for contention in buffered, direct networks is derived and found to agree closely with simulations, and it is shown that a much larger fraction of the resulting performance improvement arises from the reduction in bandwidth requirements than from the decrease in latency.
Evaluation of the Raw microprocessor: an exposed-wire-delay architecture for ILP and streams
- M. Taylor, Walter Lee, A. Agarwal
- Computer ScienceProceedings. 31st Annual International Symposium…
- 19 June 2004
The evaluation attempts to determine the extent to which Raw succeeds in meeting its goal of serving as a more versatile, general-purpose processor, and proposes a new versatility metric that uses it to discuss the generality of Raw.
Baring It All to Software: Raw Machines
The most radical of the architectures that appear in this issue are Raw processors-highly parallel architectures with hundreds of very simple processors coupled to a small portion of the on-chip memory, allowing synthesis of complex operations directly in configured hardware.
An evaluation of directory schemes for cache coherence
- A. Agarwal, R. Simoni, J. Hennessy, M. Horowitz
- Computer Science The 15th Annual International Symposium on…
- 17 May 1988
The problem of cache coherence in shared-memory multiprocessors is addressed using two basic approaches: directory schemes and snoopy cache systems. Directory schemes for cache coherence are…
ATAC: A 1000-core cache-coherent processor with on-chip optical network
- George Kurian, Jason E. Miller, A. Agarwal
- Computer Science19th International Conference on Parallel…
- 11 September 2010
ATAC, a new multicore architecture with integrated optics, and ACKwise, a novel cache coherence protocol designed to leverage ATAC's strengths are presented, showing that ATAC withACKwise out-performs a chip with conventional interconnect and cache coherent protocols.
Dynamic knobs for responsive power-aware computing
- H. Hoffmann, Stelios Sidiroglou, Michael Carbin, Sasa Misailovic, A. Agarwal, M. Rinard
- Computer Science, EngineeringASPLOS XVI
- 5 March 2011
The experimental results show that PowerDial can enable benchmark applications to execute responsively in the face of power caps that would otherwise significantly impair responsiveness, and can significantly reduce the number of machines required to service intermittent load spikes, enabling reductions in power and capital costs.